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multiple range, 16-/12-bit, bipolar/unipolar voltage output dacs with 2 ppm/c reference data sheet ad5761r / ad5721r rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2014C2015 analog devices, inc. all rights reserved. technical support www.analog.com features 8 software-programmable output ranges: 0 v to 5 v, 0 v to 10 v, 0 v to 16 v, 0 v to 20 v, 3 v, 5 v, 10 v, and ?2.5 v to +7.5 v; 5% overrange low drift 2.5 v reference: 2 ppm/c typical total unadjusted error (tue): 0.1% fsr maximum 16-bit accuracy: 2 lsb maximum guaranteed monotonicity: 1 lsb maximum single channel, 16-/12-bit dacs settling time: 7.5 s typical integrated reference buffers low noise: 35 nv/hz low glitch: 1 nv-sec (0 v to 5 v range) 1.7 v to 5.5 v digital supply range asynchronous updating via ldac asynchronous reset to zero scale/midscale dsp-/microcontroller-compatible serial interface robust 4 kv hbm esd rating 16-lead, 3 mm 3 mm lfcsp package 16-lead tssop package operating temperature range: ?40c to +125c applications industrial automation instrumentation, data acquisition open-/closed-loop servo control, process control programmable logic controllers general description the ad5761r / ad5721r are single channel, 16-/12-bit serial input, voltage output, digital-to-analog converters (dacs). they operate from single supply voltages from 4.75 v to 30 v or dual supply voltages from ?16.5 v to 0 v v ss and 4.75 v to 16.5 v v dd . the integrated output amplifier, reference buffer, and reference provide a very easy to use, universal solution. the devices offer guaranteed monotonicity, integral nonlinearity (inl) of 2 lsb maximum, 35 nv/hz noise, and 7.5 s settling time on selected ranges. the ad5761r / ad5721r use a serial interface that operates at clock rates of up to 50 mhz and are compatible with dsp and microcontroller interface standards. double buffering allows the asynchronous updating of the dac output. the input coding is user-selectable twos complement or straight binary. the asynchronous reset function resets all registers to their default state. the output range is user selectable, via the ra[2:0] bits in the control register. the devices available in a 3 mm 3 mm lfcsp package and a 16-lead tssop package offer guaranteed specifications over the ?40c to +125c industrial temperature range. functional block diagram 12-bit/ 16-bit dac ldac v out reference buffers sdi sclk sync sdo reset v dd v ss dv cc input shift register and control logic dgnd agnd ad5761r/ad5721r clear input reg dac reg 12/16 12/16 2.5v reference alert v refin / v refout dnc notes 1. dnc = do not connect. do not connect to this pin. 12355-001 0v to 5v 0v to 10v 0v to 16v 0v to 20v 3v 5v 10v ? 2.5v to +7.5v figure 1.
ad5761r/ad5721r data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specificatio ns ..................................................................................... 3 ac performance characteristics ................................................ 6 timing characteristics ................................................................ 7 timing diagrams .......................................................................... 7 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configurations and function descriptions ......................... 10 typical performance characterstics ............................................. 12 terminology .................................................................................... 23 theory of operation ...................................................................... 25 digital - to - analog converter .................................................... 25 transfer function ....................................................................... 25 dac architecture ....................................................................... 25 serial interface ............................................................................ 26 hardware control pins .............................................................. 26 therma l hysteresis .................................................................... 27 register details ............................................................................... 28 input shift register .................................................................... 28 control register ......................................................................... 29 readback control register ....................................................... 30 up date dac register from input register ............................. 31 readback dac register ............................................................ 31 write and update dac register .............................................. 31 readback input register ............................................................ 32 disa ble daisy - chain functionality .......................................... 32 software data reset ................................................................... 32 software full reset ..................................................................... 33 no operation registers ............................................................. 33 applications information .............................................................. 34 ty pical operating circuit ......................................................... 34 power supply considerations ................................................... 34 evaluation board ........................................................................ 34 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35 revision history 5 /1 5 rev. 0 to rev. a added lfcsp package ....................................................... universal changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 6 changes to table 4 ............................................................................ 9 added figure 6 and table 6; renumbered sequentially ........... 11 changes to figure 21 to figure 24 ................................................ 14 changes to figure 35 ...................................................................... 16 changes to figure 37 ...................................................................... 17 changes to figure 50 ...................................................................... 19 changes to figure 58 to figure 60 ................................................ 20 changes to figure 61 to figure 66 ................................................ 21 changes to figure 69 ...................................................................... 22 added figure 71 ............................................................................. 22 changes to terminology section ................................................. 23 changes to digital - to - analog conv erter section and internal reference section ........................................................................... 25 changes to asynchronous clear function ( clear ) section ...... 27 changes to table 12 ....................................................................... 29 changes to power supply considerations section and figure 77 .......................................................................................... 34 added figure 79 ............................................................................. 3 5 updated outline dimension s ....................................................... 3 5 c hanges to ordering guide .......................................................... 3 5 11/14 revision 0: initial version rev. a | page 2 of 35
data sheet ad5761r/ad5721r specifications v dd 1 = 4.75 v to 30 v, v ss 1 = ?16.5 v to 0 v, agnd = dgnd = 0 v, v refin /v refout = 2.5 v external, dv cc = 1.7 v to 5.5 v, r load = 1 k ? for all ranges except 0 v to 16 v and 0 v to 20 v for which r load = 2 k ? , c load = 200 pf, all specifications t min to t max , unless otherwise noted. table 1 . parameter 2 min typ max unit test conditions/comments static performance external reference 3 and internal reference, outputs unloaded programmable output ranges 0 5 v 0 10 v 0 16 v 0 20 v ?2.5 +7.5 v ?3 +3 v ?5 +5 v ?10 +10 v ad5761r resolution 16 bits relative accuracy, inl a grade ?8 +8 lsb external reference 3 and internal reference b grade 4 ?2 +2 lsb all ranges except 0 v to 16 v and 0 v to 20 v, v refin /v refout = 2.5 v exte rnal and internal reference differential nonlinearity, dnl ?1 +1 lsb ad5721r resolution 12 bits relative accuracy, inl b grade ?0.5 +0.5 lsb external reference 3 and internal reference differential nonlinearity, dnl ?0.5 +0.5 lsb zero - scale error ?6 +6 mv all ranges except 10 v and 0 v to 20 v, external reference 3 ?10 +10 mv 0 v to 20 v, 10 v ranges, external reference 3 ?6 +6 mv all ranges except 5 v, 10 v and 0 v to 20 v, internal reference ?8 +8 mv 5 v range, internal reference ?9 +9 mv 0 v to 20 v range, internal reference ?13 +13 mv 10 v range, internal reference zero - scale temperature coefficient (tc) 5 5 v/c unipolar ranges, external reference 3 and internal reference 15 v/c bipolar ranges, external reference 3 and internal reference bipolar zero error ?5 +5 mv all bipolar ranges except 10 v ?7 +7 mv 10 v output range bipolar zero tc 5 2 v/c 3 v range, external reference 3 and internal reference 5 v/c all bipolar ranges except 3 v range, external reference 3 and internal reference offset error ?6 +6 mv all ranges except 10 v and 0 v to 20 v, external reference 3 ?10 +10 mv 0 v to 20 v, 10 v ranges, external reference 3 ?6 +6 mv all ranges except 5 v, 10 v, and 0 v to 20 v; internal reference ?8 +8 mv 5 v range, internal reference ?9 +9 mv 0 v to 20 v range, internal reference ?13 +13 mv 10 v range, internal reference rev. a | page 3 of 35
ad5761r/ad5721r data sheet parameter 2 min typ max unit test conditions/comments offset error tc 5 5 v/c unipolar ranges, external reference 3 and internal reference 15 v/c bipolar ranges, external reference 3 and internal reference gain error ?0.1 +0.1 % fsr external reference 3 ?0.15 +0.15 % fsr internal reference gain error tc 5 1.5 ppm fsr/c external reference 3 and internal reference tue ?0.1 +0.1 % fsr external reference 3 ?0.15 +0.15 % fsr internal reference reference input (external) 5 reference input voltage (v ref ) 2.5 v 1% for specified performance input current ?2 0.5 +2 a reference range 2 3 v reference output (internal) 5 output voltage 2.5 v 3 mv, at ambient temperature voltage reference tc 2 5 ppm/c output impedance 25 k? output voltage noise 6 v p -p 0.1 hz to 10 hz noise spectral density 10 nv/hz at ambient; f = 10 khz line regulation 6 v/v at ambient thermal hysteresis 80 ppm first temperature cycle start - up time 3.5 ms coming out of power - down mode with a 10 nf capacitor on the v refin /v refout pin to improve noise performance; outputs unloaded output characteristics 5 output voltage range ?v out +v out see table 7 for the different output voltage ranges available ?10 +10 v v dd /v ss = 11 v, 10 v output range ?10.5 +10.5 v v dd /v ss = 11 v, 10 v output range with 5% overrange capacitive load stability 1 nf headroom 0.5 1 v r load = 1 k? for all ranges except 0 v to16 v and 0 v to 20 v ranges (r load = 2 k ? ) output voltage tc 3 ppm fsr/c 10 v range, external reference short - circuit current 25 ma short on the v out pin resistive load 1 k? all ranges except 0 v to16 v and 0 v to 20 v 2 k? 0 v to 16 v, 0 v to 20 v ranges load regulation 0.3 mv/ma outputs unloaded dc output impedance 0.5 ? outputs unloaded logic inputs 5 dv cc = 1.7 v to 5.5 v, jedec compliant input voltage high, v ih 0.7 dv cc v low, v il 0.3 dv cc v input current leakage current ?1 +1 a sdi, sclk, sync ?1 +1 a ldac , clear , reset pins held high ?55 a ldac , clear , reset pins held low pin capacitance 5 pf per pin, outputs unloaded rev. a | page 4 of 35
data sheet ad5761r/ad5721r parameter 2 min typ max unit test conditions/comments logic outputs (sdo, alert ) 5 output voltage low, v ol 0.4 v dv cc = 1.7 v to 5.5 v, sinking 200 a high, v oh dv cc ? 0.5 v dv cc = 1.7 v to 5.5 v, sourcing 200 a high impedance, sdo pin leakage current ?1 +1 a pin capacitance 5 pf power requirements v dd 4.75 30 v v ss ?16.5 0 v dv cc 1.7 5.5 v i dd 5.1 6.5 ma outputs unloaded, external reference i ss 1 3 ma outputs unloaded di cc 0.005 1 a v ih = dv cc , v il = dgnd power dissipation 67.1 mw 11 v operation, outputs unloaded, tssop package dc power supply rejection ratio (psrr) 5 0.1 mv/v v dd 10%, v ss = 15 v 0.1 mv/v v ss 10%, v dd = +15 v ac psrr 5 65 db v dd 200 mv, 50 hz/60 hz, v ss = 15 v, internal reference, c load = 100 nf 65 db v ss 200 mv, 50 hz/60 hz, v dd = +15 v, internal reference, c load = 100 nf 80 db v dd 200 mv, 50 hz/60 hz, v ss = 15 v, external reference, c load = unloaded 80 db v ss 200 mv, 50 hz/60 hz, v dd = +15 v, external reference, c load = unloaded 1 for specified performance, headroom requirement is 1 v. 2 temperature range: 40c to +125c, typical at +25c . 3 external reference means 2 v to 2.85 v with overrange and 2 v to 3 v without over range . 4 integral n onlinearity e rror is specified at 4 lsb (min/max) for 16 v and 20 v ranges with v refin /v refout = 2.5 v external and internal, and for all ranges with v refin /v refout = 2 v to 2.85 v with overrange and 2 v to 3 v without overrange . 5 guaranteed by design and characterization , not production tested. rev. a | page 5 of 35
ad5761r/ad5721r data sheet ac performance chara cteristics v dd 1 = 4.75 v to 30 v, v ss 1 = ?16.5 v to 0 v, agnd = dgnd = 0 v, v refin /v refout = 2.5 v external, dv cc = 1.7 v to 5.5 v, r load = 1 k ? for all ranges except 0 v to 16 v a nd 0 v to 20 v for which r load = 2 k ? , c load = 200 pf, all specifications t min to t max , unless otherwise noted. table 2 . parameter 2 min typ max unit test conditions/comments dynamic performance 3 output voltage settling time 9 12.5 s 20 v step to 1 lsb at 16 - bit resolution 7.5 8.5 s 10 v step to 1 lsb at 16 - bit resolution 5 s 512 lsb step to 1 lsb at 16 - bit resolution digital -to - analog glitch impulse 8 nv - sec 10 v range 1 nv - sec 0 v to 5 v range glitch impulse peak amplitude 15 mv 10 v range 10 mv 0 v to 5 v range power - on glitch 100 mv p -p digital feedthrough 0.6 nv - sec output noise 0.1 hz to 10 hz bandwidth 15 v p -p 100 khz bandwidth 45 v rms 0 v to 20 v and 0 v to 16 v ranges, 2.5 v external reference 35 v rms 0 v to 10 v, 10 v, and ?2.5 v to +7.5 v ranges, 2.5 v external reference 25 v rms 5 v range, 2.5 v external reference 15 v rms 0 v to 5 v and 3 v ranges, 2.5 v external reference output noise spectral density , at 10 khz 80 nv/hz 10 v range, 2.5 v external reference 35 nv/hz 3 v range, 2.5 v external reference 70 nv/hz 5 v, 0 v to 10 v, and ?2.5 v to +7.5 v ranges, 2.5 v external reference 110 nv/hz 0 v to 20 v range, 2.5 v external reference 90 nv/hz 0 v to 16 v range, 2.5 v external reference 45 nv/hz 0 v to 5 v range, 2.5 v external reference total harmonic distortion (thd) 4 ?87 db 2.5 v external reference, 1 khz tone signal -to - noise ratio (snr) 92 db at ambient, 2.5 v external reference, bw = 20 khz, f out = 1 khz peak harmonic or spurious noise (sfdr) 92 db at ambient, 2.5 v external reference, bw = 20 khz, f out = 1 khz signal -to - noise - and - distortion (sinad) ratio 85 db at ambient, 2.5 v external reference, bw = 20 khz, f out = 1 khz 1 for specified performance, headroom requirement is 1 v. 2 temperature range: ?40c to +125c, typical at +25c . 3 guaranteed by design and characterization, not production tested. 4 digitally generated sine wave at 1 khz. rev. a | page 6 of 35
data sheet ad5761r/ad5721r timing characteristi cs dv cc = 1.7 v to 5.5 v, all specifications t min to t max , unless otherwise noted. table 3 . parameter limit at t min , t max unit description t 1 1 20 ns min sclk cycle time t 2 10 ns min sclk high time t 3 10 ns min sclk low time t 4 15 ns min sync falling edge to sclk falling edge setup time t 5 10 ns min sclk falling edge to sync rising edge time t 6 20 ns min minimum sync high time (write mode) t 7 5 ns min data setup time t 8 5 ns min data hold time t 9 10 ns min ldac falling edge to sync falling edge t 10 20 ns min sync rising edge to ldac falling edge t 11 20 ns min ldac pulse width low t 12 9 s typ dac output settling time, 20 v step to 1 lsb at 16 - bit resolution (see table 2 ) 7.5 s typ dac output settling time, 10 v step to 1 lsb at 16 - bit resolution t 13 20 ns min cl ear pulse width low t 14 200 ns typ cl ear pulse activation time t 15 10 ns min sync rising edge to sclk falling edge t 16 40 ns max sclk rising edge to sdo valid (c l_sdo 2 = 15 pf) t 17 50 ns min minimum sync high time (readback/daisy - chain mode) 1 maximum sclk frequenc y is 50 mhz for write mode and 33 mhz for readback mode. 2 c l _ sdo is the capacitive load on the sdo output. timing diagrams d b 2 3 s c l k s y n c s d i l d a c c lea r v out v out v out 4 2 2 1 d b 0 t 1 2 t 1 2 t 1 0 t 1 1 t 1 4 t 1 3 t 9 t 8 t 7 t 4 t 6 t 3 t 2 t 1 t 5 12355-002 figure 2 . serial interface timing diagram rev. a | page 7 of 35
ad5761r/ad5721r data sheet t 4 t 10 t 16 t 8 t 7 t 11 t 3 t 2 t 5 t 1 t 15 ldac sdo sdi sync sclk 8 4 4 2 db0 db23 db0 db23 db23 input word for dac n undefined input word for dac n ? 1 input word for dac n db0 t 17 12355-003 figure 3 . daisy - chain timing diagram sdo sdi sync sclk 24 24 db23 db0 db23 db0 selected register data clocked out undefined nop condition input word specifies register to be read 1 1 db23 db0 db23 db0 t 17 12355- 004 figure 4 . readback timing diagram rev. a | page 8 of 35
data sheet ad5761r/ad5721r absolute maximum rat ings t a = 25c, unless otherwise noted. transient currents of up to 200 ma do not cause silicon controlled rectifier (scr) latch - up. table 4 . parameter rating v dd to agnd ? 0.3 v to +34 v v ss to agnd +0.3 v to ? 17 v v dd to v ss ?0.3 v to +34 v dv cc to dgnd ? 0.3 v to +7 v digital inputs to dgnd ? 0.3 v to dv cc + 0.3 v or 7 v (whichever is less) digital outputs to dgnd ? 0.3 v to dv cc + 0.3 v or 7 v (whichever is less) v refin /v refout to dgnd ? 0.3 v to +7 v v out to agnd v ss to v dd agnd to dgnd ?0.3 v to +0.3 v operating temperature range, t a industrial ? 40c to +125c storage temperature range ? 65c to +150c junction temperature, t j max 150c 16- lead tssop package ja thermal impedance 113c/w 1 jc thermal impedance 28c/w 16- lead lfcsp package ja thermal impedance 75 c/w 1 jc thermal impedance 4.5 c/w 2 power dissipation (t j max ? t a )/ ja lead temperature jedec industry standard soldering j - std -020 esd (human body model) 4 kv 1 jedec 2s2p test board, still air (0 m/sec airflow). 2 measured to exposed paddle, with infinite heat sink on package top surface. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond th e maximum operating conditions for extended periods may affect product reliability. esd caution rev. a | page 9 of 35
ad5761r/ad5721r data sheet rev. a | page 10 of 35 pin configurations and function descriptions 1 2 3 4 5 6 7 8 agnd v out v ss v refin/ v refout v dd 16 15 14 13 12 11 10 9 sdi dgnd sdo dv cc dnc sclk sync clear reset ldac alert 12355- 006 top view (not to scale) ad5761r/ ad5721r notes 1. dnc = do not connect. do not connect to this pin. figure 5. 16-lead tssop pin configuration table 5. 16-lead tssop pin function descriptions pin no. mnemonic description 1 alert active low alert. this pin is asserted low when the die temperature exceeds approximately 150c, or when an output short circuit or a brownout occurs. this pin is also asserted low during power-up, a full software reset, or a hardware reset, for which a write to the control register asserts the pin high. 2 clear falling edge clear input. asserting this pin sets the dac register to zero scale, midscale, or full-scale code (user selectable) and updates the dac output. this pin can be left floating because there is an internal pull-up resistor. 3 reset active low reset input. asserting this pin returns the ad5761r / ad5721r to their default power-on status where the output is clamped to ground and the output buffer is powered do wn. this pin can be left floating because there is an internal pull-up resistor. 4 v refin /v refout internal reference voltage output and external reference voltage input. for specified performance, v refin /v refout = 2.5 v. connect a 10 nf capacitor with the internal reference to minimize the noise. 5 agnd ground reference pin for analog circuitry. 6 v ss negative analog supply connection. a voltage in the rang e of ?16.5 v to 0 v can be connected to this pin. for unipolar output ranges, connect this pin to 0 v. v ss must be decoupled to agnd. 7 v out analog output voltage of the dac. the output amplifie r is capable of directly driving a 2 k, 1 nf load. 8 v dd positive analog supply connection. a voltage in the rang e of 4.75 v to 30 v can be connected to this pin for unipolar output ranges. bipolar o utput ranges accept a voltage in the range of 4.75 v to 16.5 v. v dd must be decoupled to agnd. 9 dnc do not connect. do not connect to this pin. 10 sdo serial data output. this pin clocks data from the serial register in daisy-chain or readback mode. data is clocked out on the rising edge of sclk and is valid on the falling edge of sclk. 11 ldac load dac. this logic input updates the dac register and, consequently, the analog output. when tied permanently low, the dac register is updated when the input register is updated. if ldac is held high during the write to the input register, the dac output register is not updated, and the dac output update is held off until the falling edge of ldac . this pin can be left floating because there is an internal pull-up resistor. 12 sdi serial data input. data must be valid on the falling edge of sclk. 13 sync active low synchronization input. this pin is the frame synchronization signal for the serial interface. while sync is low, data is transferred in on the falling edge of sclk. data is latched on the rising edge of sync . 14 sclk serial clock input. data is clocked in to the input shift register on the falling edge of sclk. this pin operates at clock speeds of up to 50 mhz. 15 dv cc digital supply. the voltage range is from 1.7 v to 5.5 v. the applied voltage sets the voltage at which the digital interface operates. 16 dgnd digital ground.
data sheet ad5761r/ad5721r rev. a | page 11 of 35 12335-106 12 11 10 1 3 4 9 2 6 5 7 8 1 6 1 5 1 4 1 3 ad5761r/ ad5721r top view (not to scale) notes 1. dnc = do not connect. 2. the exposed pad must be me chanically connected to the pcb copper plane for optim a l thermal performance. the exposed pad can be left electrically floating. reset v refin /v refout agnd v ss sclk dv cc dgnd alert clea r sync sdi ldac v out v dd dnc sdo figure 6. 16-lead lfcsp pin configuration table 6. 16-lead lfcsp pin function descriptions pin no. mnemonic description 1 reset active low reset input. asserting this pin returns the ad5761r / ad5721r to their default power-on status where the output is clamped to ground and the output buffer is powered do wn. this pin can be left floating because there is an internal pull-up resistor. 2 v refin /v refout internal reference voltage output and external reference voltage input. for specified performance, v refin /v refout = 2.5 v. connect a 10 nf capacitor with the internal reference to minimize the noise. 3 agnd ground reference pin for analog circuitry. 4 v ss negative analog supply connection. a voltage in the rang e of ?16.5 v to 0 v can be connected to this pin. for unipolar output ranges, connect this pin to 0 v. v ss must be decoupled to agnd. 5 v out analog output voltage of the dac. the output amplifie r is capable of directly driving a 2 k, 1 nf load. 6 v dd positive analog supply connection. a voltage in the rang e of 4.75 v to 30 v can be connected to this pin for unipolar output ranges. bipolar o utput ranges accept a voltage in the range of 4.75 v to 16.5 v. v dd must be decoupled to agnd. 7 dnc do not connect. do not connect to this pin. 8 sdo serial data output. this pin clocks data from the serial register in daisy-chain or readback mode. data is clocked out on the rising edge of sclk and is valid on the falling edge of sclk. 9 ldac load dac. this logic input updates the dac regist er and, consequently, the analog output. when tied permanently low, the dac register is updated when the input register is updated. if ldac is held high during the write to the input register, the dac output register is not updated, and the dac output update is held off until the falling edge of ldac . this pin can be left floating because there is an internal pull-up resistor. 10 sdi serial data input. data must be valid on the falling edge of sclk. 11 sync active low synchronization input. this pin is the frame synchronization signal for the serial interface. while sync is low, data is transferred in on the falling edge of sclk. data is latched on the rising edge of sync . 12 sclk serial clock input. data is clocked in to the input shift register on the falling edge of sclk. this pin operates at clock speeds of up to 50 mhz. 13 dv cc digital supply. the voltage range is from 1.7 v to 5.5 v. the applied voltage sets the voltage at which the digital interface operates. 14 dgnd digital ground. 15 alert active low alert. this pin is asserted low when the die temperature exceeds approximately 150c, or when an output short circuit or a brownout occurs. this pin is also asserted low during power-up, a full software reset, or a hardware reset, for which a write to the control register asserts the pin high. 16 clear falling edge clear input. asserting this pin sets the dac register to zero scale, midscale, or full-scale code (user selectable) and updates the dac output. this pin can be left floating because there is an internal pull-up resistor. epad exposed pad. the exposed pad must be mechanically co nnected to the pcb copper plane for optimal thermal performance. the exposed pad can be left electrically floating.
ad5761r/ad5721r data sheet rev. a | page 12 of 35 typical performance characterstics ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 10000 20000 30000 40000 50000 60000 dac code inl error (lsb) +5v span +10v span +16v span +20v span v dd = +21v v ss =?11v 12355-007 figure 7. ad5761r inl error vs. dac code, unipolar output ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 500 1000 1500 2000 2500 3000 3500 4000 dac code inl error (lsb) +5v span +10v span +16v span +20v span v dd = +21v v ss = ?11v 12355-008 figure 8. ad5721r inl error vs. dac code, unipolar output ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 10000 20000 30000 40000 50000 60000 dac code inl error (lsb) 3v span 5v span 10v span ?2.5v to +7.5v span v dd = +21v v ss = ?11v 12355-009 figure 9. ad5761r inl error vs. dac code, bipolar output ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 500 1000 1500 2000 2500 3000 3500 4000 dac code inl error (lsb) v dd = +21v v ss = ?11v 3v span 5v span 10v span ?2.5v to +7.5v span 12355-010 figure 10. ad5721r inl error vs. dac code, bipolar output ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 10000 20000 30000 40000 50000 60000 dac code dnl error (lsb) v dd = +21v v ss =?11v +5v span +10v span +16v span +20v span 12355-011 figure 11. ad5761r dnl error vs. dac code, unipolar output ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 500 1000 1500 2000 2500 3000 3500 4000 dac code dnl error (lsb) +5v span +10v span +16v span +20v span v dd = +21v v ss = ?11v 12355-012 figure 12. ad5721r dnl error vs. dac code, unipolar output
data sheet ad5761r/ad5721r rev. a | page 13 of 35 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 10000 20000 30000 40000 50000 60000 dac code dnl error (lsb) v dd = +21v v ss =?11v 3v span 5v span 10v span ?2.5v to +7.5v span 12355-013 figure 13. ad5761r dnl error vs. dac code, bipolar output ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 500 1000 1500 2000 2500 3000 3500 4000 dac code dnl error (lsb) v dd = +21v v ss = ?11v 3v span 5v span 10v span ?2.5v to +7.5v span 12355-014 figure 14. ad5721r dnl error vs. dac code, bipolar output ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 +5v u1 int max inl +5v u2 ext max inl 10v u1 int max inl 10v u2 ext max inl +5v u1 int min inl v dd = +21v v ss = ?11v i n l error (lsb) +5v u2 ext min inl 10v u1 int min inl 10v u2 ext min inl ?40 ?20 0 25 50 85 105 125 temperature (c) 12355-015 figure 15. inl error vs. temperature ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?40 ?20 0 25 50 85 105 125 dnl error (lsb) +5v u2 ext max dnl 10v u2 ext max dnl +5v u1 int max dnl 10v u1 int max dnl +5v u2 ext min dnl 10v u2 ext min dnl +5v u1 int min dnl 10v u1 int min dnl temperature ( c) v dd = +21v v ss = ?11v 12355-016 figure 16. dnl error vs. temperature ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 +5v span v dd /v ss = +6v/?1v 10v span v dd /v ss = +11v/?11v v dd /v ss = +7.5v/?1v v dd /v ss = +12.5v/?12.5v v dd /v ss = +10v/?1v v dd /v ss = +13.5v/?13.5v v dd /v ss = +12.5v/?1v v dd /v ss = +14.5v/?14.5v v dd /v ss = +16.5v/?1v v dd /v ss = +16.5v/?16.5v supply voltage (v) inl error (lsb) v dd = +21v v ss = ?11v t a = 25 c no load +5v u2 ext max inl +5v u2 ext min inl +5v u1 int max inl +5v u1 int min inl 10v u2 ext max inl 10v u2 ext min inl 10v u1 nt max inl 10v u1 int min inl 12355-017 figure 17. inl error vs. supply voltage ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 +5v span v dd /v ss = +6v/?1v 10v s pan v dd /v ss = + 11v/?11v v dd /v ss = +7.5v/?1v v dd /v ss = +12.5v/?12.5v v dd /v ss = +10v/?1v v dd /v ss = +13.5v/?13.5v v dd /v ss = +12.5v/?1v v dd /v ss = +14.5v/?14.5v v dd /v ss = +16.5v/?1v v dd /v ss = +16.5v/?16.5v supply voltage (v) dnl error (lsb) v dd = +21v v ss = ?11v t a = 25 c no load +5v u2 ext max dnl +5v u2 ext min dnl +5v u1 int max dnl +5v u1 int min dnl 10v u2 ext max dnl 10v u2 ext min dnl 10v u1 nt max dnl 10v u1 int min dnl 12355-018 figure 18. dnl error vs. supply voltage
ad5761r/ad5721r data sheet rev. a | page 14 of 35 ?3 ?2 ?1 0 1 2 3 2.00 2.25 2.50 2.75 3.00 inl error (lsb) reference voltage (v) v dd = +21v v ss = ?11v max inl, +5v span max inl, 10v span min inl, +5v span min inl, 10v span 12355-019 figure 19. inl error vs. reference voltage ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 12355-020 2.00 2.50 2.25 2.75 3.00 dnl error (lsb) reference voltage (v) v dd = +21v v ss = ?11v max dnl, 10v span max dnl, +5v span min dnl, 10v span min dnl, +5v span figure 20. dnl error vs. reference voltage 12355-021 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 ?40 ?20 0 255085105125 temperature (c) zero-scale error (v) v dd = +21v v ss = ?11v +5v u1 ext +5v u2 int 10v u1 ext 10v u2 int figure 21. zero-scale error vs. temperature ?40 ?20 02550 85 105 125 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 midscale error (v) temperature (c) v dd = +21v v ss = ?11v 12355-022 +5v u1 ext +5v u2 int 10v u1 ext 10v u2 int figure 22. midscale error vs. temperature 12355-023 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 ?40 ?20 0 25 50 85 105 125 temperature (c) full-scale error (v) v dd = +21v v ss = ?11v +5v u1 ext +5v u2 int 10v u1 ext 10v u2 int figure 23. full-scale error vs. temperature ?40 ?20 0 25 50 85 105 125 temperature (c) ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 gain error (%fsr) v dd = +21v v ss = ?11v 12355-024 +5v u1 ext +5v u2 int 10v u1 ext 10v u2 int figure 24. gain error vs. temperature
data sheet ad5761r/ad5721r rev. a | page 15 of 35 ?0.0050 ?0.0045 ?0.0040 ?0.0035 ?0.0030 ?0.0025 ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 +5v span v dd /v ss = +6v/?1v 10v span v dd /v ss = +11v/?11v v dd /v ss = +7.5v/?1v v dd /v ss = +12.5v/?12.5v v dd /v ss = +10v/?1v v dd /v ss = +13.5v/?13.5v v dd /v ss = +12.5v/?1v v dd /v ss = +14.5v/?14.5v v dd /v ss = +16.5v/?1v v dd /v ss = +16.5v/?16.5v supply voltage (v) +5v u2 ext +5v u1 int 10v u2 ext 10v u1 int zero-scale error (v) t a = 25c v ref = 2.5v 12355-025 figure 25. zero-scale error vs. supply voltage ?0.0030 ?0.0025 ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 midscale error (v) +5v span v dd /v ss = +6v/?1v 10v span v dd /v ss = +11v/?11v v dd /v ss = +7.5v/?1v v dd /v ss = +12.5v/?12.5v v dd /v ss = +10v/?1v v dd /v ss = +13.5v/?13.5v v dd /v ss = +12.5v/?1v v dd /v ss = +14.5v/?14.5v v dd /v ss = +16.5v/?1v v dd /v ss = +16.5v/?16.5v supply voltage (v) +5v u2 ext +5v u1 int 10v u2 ext 10v u1 int t a = 25c v ref = 2.5v 12355-026 figure 26. midscale error vs. supply voltage ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 +5v span v dd /v ss = +6v/?1v 10v span v dd /v ss = +11v/?11v v dd /v ss = +7.5v/?1v v dd /v ss = +12.5v/?12.5v v dd /v ss = +10v/?1v v dd /v ss = +13.5v/?13.5v v dd /v ss = +12.5v/?1v v dd /v ss = +14.5v/?14.5v v dd /v ss = +16.5v/?1v v dd /v ss = +16.5v/?16.5v supply voltage (v) +5v u2 ext +5v u1 int 10v u2 ext 10v u1 int full-scaleerror (v) t a = 25c v ref = 2.5v 12355-027 figure 27. full-scale error vs. supply voltage ?0.030 ?0.025 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0.025 0.030 gain error (%fsr) +5v span v dd /v ss = +6v/?1v 10v span v dd /v ss = + 11v/?11v v dd /v ss = +7.5v/?1v v dd /v ss = +12.5v/?12.5v v dd /v ss = +10v/?1v v dd /v ss = +13.5v/?13.5v v dd /v ss = +12.5v/?1v v dd /v ss = +14.5v/?14.5v v dd /v ss = +16.5v/?1v v dd /v ss = +16.5v/?16.5v supply voltage (v) +5v u2 ext +5v u1 int 10v u2 ext 10v u1 int t a = 25c v ref = 2.5v 12355-028 figure 28. gain error vs. supply voltage ?0.005 ?0.003 ?0.001 0.001 0.003 0.005 2.0 2.5 3.0 +5v span 10v span reference voltage (v) zero-scale error (v) v dd = +21v v ss = ?11v t a = 25 ?c 12355-029 figure 29. zero-scale error vs. reference voltage ?0.0010 ?0.0008 ?0.0006 ?0.0004 ?0.0002 0 0.0002 0.0004 0.0006 0.0008 0.0010 2.0 2.5 3.0 reference voltage (v) midscale error (v) +5v span 10v span v dd = +21v v ss = ?11v t a = 25 c 12355-030 figure 30. midscale error vs. reference voltage
ad5761r/ad5721r data sheet rev. a | page 16 of 35 ?0.005 ?0.003 ?0.001 0.001 0.003 0.005 2.0 2.5 3.0 reference voltage (v) full-scale error (v) +5v span 10v span v dd = +21v v ss = ?11v t a = 25 c 12355-031 figure 31. full-scale error vs. reference voltage ?0.05 ?0.03 ?0.01 0.01 0.03 0.05 2.0 2.5 3.0 +5v span 10v span reference voltage (v) gain error (%fsr) v dd = +21v v ss = ?11v t a = 25c 12355-032 figure 32. gain error vs. reference voltage ?0.05 ?0.03 ?0.01 0.01 0.03 0.05 tue (%fsr) 0 10000 20000 30000 40000 50000 60000 +5v span_int +16v span_int +5v span_ext +16v span_ext +10v span_int +20v span_int +10v span_ext +20v span_ext t a = 25c code 12355-033 figure 33. tue vs. code, unipolar output ?0.05 ?0.03 ?0.01 0.01 0.03 0.05 0 10000 20000 30000 40000 50000 60000 5v span_int 10v span_int ?2.5v to +7.5v span_int 3v span_int 5v span_ext 10v span_ext ?2.5v to +7.5v span_ext 3v span_ext code tue (%fsr) 12355-034 t a = 25c figure 34. tue vs. code, bipolar output 0 0.01 0.02 0.03 0.04 0.05 0.06 ?40 ?20 0 20 40 60 80 100 120 +5v_u1_extref +5v_u2_intref +5v_u3_intref 10v_u1_extref 10v_u2_intref 10v_u3_intref temperature ( ? c) tue (%fsr) v dd = +21v v ss = ?11v 12355-035 figure 35. tue vs. temperature 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.020 0.022 0.024 0.026 0.028 0.030 tue (%fsr) +5v span v dd /v ss = +6v/?1v 10v span v dd /v ss = + 11v/?11v v dd /v ss = +7.5v/?1v v dd /v ss = +12.5v/?12.5v v dd /v ss = +10v/?1v v dd /v ss = +13.5v/?13.5v v dd /v ss = +12.5v/?1v v dd /v ss = +14.5v/?14.5v v dd /v ss = +16.5v/?1v v dd /v ss = +16.5v/?16.5v supply voltage (v) +5v u2 ext +5v u1 int 10v u2 ext 10v u1 int t a = 25c v ref = 2.5v 12355-036 figure 36. tue vs. supply voltage
data sheet ad5761r/ad5721r rev. a | page 17 of 35 12355-037 200s/div 500mv 5v 5v sync v ref v out figure 37. reference output voltage turn on transient ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 noise (v peak) time (seconds) v dd = +21v v ss = ?11v t a = 25 ? c 12355-038 figure 38. internal reference noise (100 khz bandwidth) ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 noise (v peak) time (second) v dd = +21v v ss = ?11v t a = 25 ? c 12355-039 figure 39. internal reference noise (0.1 hz to 10 hz bandwidth) reference output noise spectral density (v/ hz) 0.00001 0.000001 0.0000001 0.00000001 0.000000001 10 100 1k frequency (hz) 10k 100k 1m av dd = 21v av ss = ?11v dv cc = 5v load = 2k ? ||200pf cap on v ref = 10nf 12355-138 figure 40. reference output noise spectral density vs. frequency 2.4998 2.5000 2.5002 2.5004 2.5006 2.5008 2.5010 2.5012 2.5014 v ss ?13.50 ?13.75 ?14.00 ?14.25 ?14.50 ?14.75 ?15.00 ?15.25 ?15.50 ?15.75 ?16.00 ?16.25 v dd 13.50 13.75 14.00 14.25 14.50 14.75 15.00 15.25 15.50 15.75 16.00 16.25 v refout (v) supply voltage (v) 12355-139 figure 41. reference output voltage (v refout ) vs. supply voltage 1.5 2.0 2.5 3.0 ?10?8?6?4?2 0 2 4 6 8 10 bipolar 10v unipolar 10v bipolar 5v unipolar 5v ?2.5v to 7.5v bipolar 3v unipolar 16v unipolar 20v load current (a) intern a l reference (v) v dd = +21v v ss = ?11v t a = 25c 12355-040 figure 42. internal reference vs. load current
ad5761r/ad5721r data sheet rev. a | page 18 of 35 2.50000 2.50025 2.50050 2.50075 2.50100 2.50125 2.50150 2.50175 2.50200 ?40 ?20 0 25 55 85 105 125 v refout (v) temperature (c) 12355-041 figure 43. reference output voltage vs. temperature 0 10 20 30 40 50 60 70 number of units temperature drift (ppm/c) 0.412 0.634 0.856 1.078 1.301 1.523 1.745 1.967 2.189 2.412 2.634 2.856 12355-042 figure 44. reference output tc ?15000 ?10000 ?5000 0 5000 10000 15000 20000 25000 30000 ?30 ?20 ?10 0 10 20 30 output voltage delt a (v) 40 source/sink current (ma) v dd = +21v v ss = ? 11v t a = 25c 10v +10v 5v +5v ?2.5v to +7.5v 3v +16v +20v 12355-043 figure 45. source and sink capability of output amplifier with positive full scale loaded ?20000 ?15000 ?10000 ?5000 0 5000 10000 15000 source/sink current (ma) output voltage delt a (v) ?30 ?20 ?10 0 10 20 30 v dd = +21v v ss = ? 11v t a = 25c 10v +10v 5v +5v ?2.5v to +7.5v 3v +16v +20v 12355-044 figure 46. source and sink capability of output amplifier with negative full scale loaded 0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008 0.0009 0.0010 012345 supply current (a) logic input voltage (v) idv cc 3v idv cc 5v v dd = +21v v ss = ?11v t a = 25 ? c load = 2k ? || 200pf internal reference 12355-045 figure 47. supply current vs. logic input voltage 12355-046 ?6 ?4 ?2 0 2 4 6 ?8.0 ?6.0 ?4.0 ?2.0 0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 v out (v) time (s) sync 5v, zero scale to full scale v dd = +21v v ss =?11v t a = 25c load = 2k ? ||200pf figure 48. full-scale settling time (rising voltage step), 5 v range
data sheet ad5761r/ad5721r rev. a | page 19 of 35 12355-047 ?6 ?4 ?2 0 2 4 6 ?8.0 ?6.0 ?4.0 ?2.0 0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 v out (v) time (s) v dd =+21v v ss =?11v t a =25 c load = 2k ? ||200pf sync 5v, full scale to zero scale figure 49. full-scale settling time (falling voltage step), 5 v range 12355-048 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 ?3?2?10123456789101112131415 time (s) v out (v) sync 10v, zero scale to full scale v dd = +21v v ss =?11v t a = 25c load = 2k ? ||200pf figure 50. full-scale settling time (rising voltage step), 10 v range 12355-049 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 ?3.0 ?1.0 1.0 3.0 5.0 7.0 9.0 11.0 13.0 15.0 time (s) sync 10v, fullscale to zero scale v out (v) v dd = +21v v ss =?11v t a = 25c load = 2k ? ||200pf figure 51. full-scale settling time (falling voltage step), 10 v range ?0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 ?2?1012345 time (s) v out (v) sync 500-code step, 5v span 12355-050 v dd = +21v v ss =?11v t a = 25c load = 2k ? ||200pf figure 52. 500-code step settling time, 5 v range ?0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20 ?2?1012345 time (s) v out (v) v dd = +21v v ss = ?11v t a = 25c load = 2k ? ||200pf sync 500-code step, 10v span 12355-051 figure 53. 500-code step settling time, 10 v range ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 ?5 0 5 10 15 20 time (s) 0nf 1nf 5nf 7nf 10nf v out (v) v dd =+21v v ss = ?11v t a = 25c load = 2k ? 12355-052 figure 54. full-scale settling time at various capacitive loads, 10 v range
ad5761r/ad5721r data sheet rev. a | page 20 of 35 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?3?2?1123456789101112131415 time (s) 0nf 1nf 5nf 7nf 10nf v out (v) v dd = +21v v ss = ?11v t a = 25 ? c load = 2k ? 12355-053 figure 55. full-scale settling time at various capacitive loads, 0 v to 5 v range ?0.010 ?0.009 ?0.008 ?0.007 ?0.006 ?0.005 ?0.004 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 0.004 0.005 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v out (v) time (s) v dd = 21v v ss = ?11v load = 2k ? ||200pf t a = 25c 12355-054 figure 56. digital-to-analog glitch energy, 5 v range 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v out (v) time (s) ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 v dd = 21v v ss = ?11v load = 2k ? ||200pf t a = 25c 12355-055 figure 57. digital-to-analog glitch energy, 10 v range 12355-156 2 v dd 20ms/div 10v 5v 20mv 10v v out v ss v refin /v refout figure 58. power-up glitch 12355-057 200s/div 5v 5v 1v 5v sclk sync sdi v out figure 59. software full reset glitch from full scale with output loaded, 0 v to 5 v range 12355-058 sclk 200s/div 5v 5v 500mv 5v sync sdi v out figure 60. software full reset glitch from midscale with output loaded, 5 v range
data sheet ad5761r/ad5721r rev. a | page 21 of 35 12355-059 sclk sync sdi v out 200s/div 5v 5v 200mv 5v figure 61. software full reset glitch from zero scale with output loaded, 0 v to 5 v range 12355-060 sclk 200s/div 5v 5v 2v 5v sync sdi v out figure 62. software full reset glitch from full scale with output loaded, 10 v range 12355-161 sclk 200s/div 5v 5v 500m v 5v sync sdi v out figure 63. software full reset glitch from midscale with output loaded, 10 v range 12355-162 sclk sdi 200s/div 5 v 5 v 2 v 5 v sync v out figure 64. software full reset glitch from zero scale with output loaded, 10 v range 12355-263 200s/div 5 v 5 v 1 v 5 v sclk sync sdi v out figure 65. output range change glitch, 0 v to 5 v range 12355-164 200s/div 5v 5v 200mv 5v sclk sync sdi v out figure 66. output range ch ange glitch, 10 v range
ad5761r/ad5721r data sheet rev. a | page 22 of 35 ?4 ?2 0 2 4 6 8 10 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 noise (vp-p) time (seconds) v dd = +21v v ss = ?11v v refin = 2.5v t a = 25 ? c noise int ref noise ext ref 12355-265 figure 67. peak-to-peak noise (voltage output noise), 0.1 hz to 10 hz bandwidth ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 noise (v rms) time (seconds) v dd = +21v v ss = ?11v v refin = 2.5v t a = 25c ?30 ?20 ?10 0 10 20 30 noise ext ref noise int ref 12355-266 figure 68. peak-to-peak noise (voltage output noise), 100 khz bandwidth 0 200 400 600 800 1000 1200 1400 1600 10 100 1k 10k 100k 1m nsd (nv/ hz) frequency (hz) dac output nsd (nv/ hz), intref, zs dac output nsd (nv/ hz), intref, ms dac output nsd (nv/ hz), intref, fs v dd = +21v v ss =?11v t a = 25c 12355-163 figure 69. dac output noise spectral density (nsd) vs. frequency, 10 v range ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 24.1 24.1 24.2 24.3 24.4 24.5 24.5 24.6 24.7 24.8 24.9 24.9 25.0 25.1 25.2 25.3 25.3 25.4 25.5 25.6 25.7 25.7 25.8 25.9 digital f eedthrough ( v p -p) time (s) t a = 25c v dd = 21v v ss =?11v dv cc =5v 2.5v ext ref load = 2k ? ||200pf 12355-168 figure 70. digital feedthrough ?160 02468101214161820 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 thd (dbv) frequency (khz) 12355-071 figure 71. total harmonic distortion
data sheet ad5761r/ad5721r terminology total unadjusted error (tue) total unadjusted error is a measure of the output error taking all the various errors into account, namely inl error, offset error, gain error, and output drift over supplies, temperature, and time. tue is expressed in % fsr. relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation, in lsb, from a straight line passing through the endpoints of the dac transfer function. a typical inl error vs. dac code plot is shown in figure 7 . differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between a ny two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. the ad5761r / ad5721r are gua ranteed monotonic. a typical dnl error vs. code plot is shown in figure 11. monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital input code. the ad5761r / ad5721r are monotonic over their full operating temperature range. bipolar zero error bipolar zero error is the deviation of the analog output from the ideal half - scale output of 0 v when the dac register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding) for the ad5761r / ad5721r . bipolar zero temperature coefficient (tc) bipolar zero tc is a measure of the change in the bipolar zero error with a change in temperature . it is expressed in v/c. zero - scale error zero - scale error is the error in the dac output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the dac register. ideally, the output voltage is negative full scale. a plot of zero - scale error vs. temperature is shown in figure 21. zero - scale error temperature coefficient (tc) zero - scale error tc is a measure of th e change in zero - scale error with a change in temperature. it is expressed in v/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset erro r temperature coefficient (tc) offset error tc is a measurement of the change in offset error with a change in temperature. it is expressed in v/c. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed in % fsr. a plot of gain error vs. temperature is shown in figure 24. gain error temperature coeff icient (tc) gain error tc is a measure of the change in gain error with changes in temperature. it is expressed in ppm fsr/c . dc power supply rejection ratio (dc psrr) dc power supply rejection ratio is a measure of the rejection of the output voltage to dc changes in the power supplies applied to the dac. it is measured for a given dc change in power supply voltage and is expressed in m v / v. ac power supply rejection rat io (ac psrr) ac power supply rejection ratio is a measure of the rejection of the output voltage to ac changes in the power supplies applied to the dac. it is measured for a given amplitude and frequency change in power supply voltage and is expressed in d ecibels. output voltage settling time output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full - scale input change. full - scale settling time is shown in figure 48 to figure 51. digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - sec and is measured when the digital input code is changed by 1 lsb at the major carry transition (see figure 56 and figure 57). glitch impuls e peak amplitude glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the dac register changes state. it is specified as the amplitude of the glitch in mv and is measured when the digital input code is changed by 1 lsb at the major carry transition. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not upda ted. it is specified in nv - sec and measured with a full - scale code change on the data bus. noise spectral density (nsd) noise spectral density is a measurement of the internally generated random noise characterized as a spectral density (nv/hz). it is mea sured by loading the dac to full scale and measuring noise at the output. it is measured in nv/hz. a plot of noise spectral density is shown in figure 69. rev. a | page 23 of 35
ad5761r/ad5721r data sheet voltage reference temperature coefficient (tc) voltage reference tc is a measure of the change in the reference output voltage with a change in temperature. the reference tc is calculated using the box method, which defines the tc as the maximum change in the reference output over a given temperature r ange expressed in ppm/c as follows: 6 _ _ _ 10 ? ? ? ? ? ? ? ? ? = range temp v v v tc nom ref min ref max ref ee v ref_max is the maximum reference output measured over the total temperature range. v ref_min is the minimum reference output measured over the total temperature range. v ref_nom is the no minal reference output voltage, 2.5 v. te mp range is the specified temperature range, ?40c to +125c. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for the ad5761r / ad5721r , it is defined as 1 2 6 2 5 2 4 2 3 2 2 log 20 ) ( v v v v v v db thd + + + + = v1 is the rms amplitude of the fundamental. v2 , v3 , v4 , v5 , and v6 are the rms amplitudes of the second through the sixth harmonics. rev. a | page 24 of 35
data sheet ad5761r/ad5721r rev. a | page 25 of 35 theory of operation digital-to-analog converter the ad5761r / ad5721r are single channel, 16-/12-bit voltage output dacs. the ad5761r / ad5721r output ranges are software selectable and can be configured as follows: ? unipolar output voltage: 0 v to 5 v, 0 v to 10 v, 0 v to 16 v, 0 v to 20 v ? bipolar output voltage: ?2.5 v to +7.5 v, 3 v, 5 v, 10 v data is written to the ad5761r / ad5721r in a 24-bit word format via a 4-wire, serial peripheral interface (spi) compatible, digital interface. the devices also offer an sdo pin to facilitate daisy-chaining and readback. transfer function the internal reference is on by default. the input coding to the dac can be straight binary or twos complement (bipolar ranges case only). therefore, the transfer function is given by ? ? ? ? ? ? ? ? ? ? ? ? ? ??? c d mvv ref out 536,65 where: v ref is 2.5 v. d is the decimal equivalent of the code loaded to the dac register as follows: 0 to 4095 for the 12-bit device. 0 to 65,535 for the 16-bit device. the values for m and c are as shown in table 7. table 7. m and c values fo r various output ranges range m c 10 v 8 4 5 v 4 2 3 v 2.4 1.2 ?2.5 v to +7.5 v 4 1 0 v to 20 v 8 0 0 v to 16 v 6.4 0 0 v to 10 v 4 0 0 v to 5 v 2 0 dac architecture the dac architecture consists of an r-2r dac followed by an output buffer amplifier. figure 72 shows a block diagram of the dac architecture. note that the reference input is buffered prior to being applied to the dac. the ad5761r / ad5721r offer a 2.5 v, 5 ppm/c maximum internal reference on chip. the output voltage range obtained from the configurable output amplifier is selected by writing to the 3 lsbs (ra[2:0]) in the control register. agnd r- 2r v refin agnd configurable output amplifier output range control v refin / v refout dac register v out 12355- 061 figure 72. dac architecture r-2r dac the architecture of the ad5761r consists of two matched dac sections. a simplified circuit diagram is shown in figure 73. the 6 msbs of the 16-bit data-word are decoded to drive 63 switches, e0 to e62, while the remaining 10 bits of the data- word drive the s0 to s9 switches of a 10-bit voltage mode r-2r ladder network. the code loaded into the dac register determines which arms of the ladder are switched between v ref and ground (agnd). the output voltage is taken from the end of the ladder and amplified afterwards to provide the selected output voltage. 2r s0 2r 2r 10-bit r-2r ladder 6 msbs decoded into 63 equal segments s1 2r s9 2r r rr e62 2r ... ... ... ... e61 2r v out v ref agnd e0 12355- 062 figure 73. dac ladder structure internal reference the ad5761r / ad5721r feature an on-chip reference. the on-chip reference is on at power-up, and this reference can be turned off by setting the software-programmable bit, db5, in the control register. table 12 shows how the state of the bit corresponds to the mode of operation. the internal reference is available at the v rfefin /v refout pin. a buffer is required if the reference output is used to drive external loads. place a capacitor in the range of 1 nf to 100 nf between the reference output and dgnd to improve the noise performance. reference buffer the ad5761r / ad5721r can operate with either an external or internal reference. the reference input has an input range of 2 v to 3 v with 2.5 v for specified performance. this input voltage is then buffered before it is applied to the dac core.
ad5761r/ad5721r data sheet rev. a | page 26 of 35 dac output amplifier the output amplifier is capable of generating both unipolar and bipolar output voltages. it is capable of driving a load of 2 k in parallel with 1 nf to agnd. the source and sink capabilities of the output amplifier are shown in figure 45. serial interface the ad5761r / ad5721r 4-wire digital interface ( sync , sclk, sdi, and sdo) is spi compatible. the write sequence begins after bringing the sync line low, and maintaining this line low until the complete data-word is loaded from the sdi pin. data is loaded in at the sclk falling edge transition (see figure 2). when sync is brought high again, the serial data-word is decoded according to the instructions in table 10. the ad5761r / ad5721r contain an sdo pin to allow the user to daisy-chain multiple devices together or to read back the contents of the registers. standalone operation the serial interface works with both a continuous and noncontinuous serial clock. a continuous sclk source can be used only when sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. the first falling edge of sync starts the write cycle. exactly 24 falling clock edges must be applied to sclk before sync is brought high again. if sync is brought high before the 24th falling sclk edge, the data written is invalid. if more than 24 falling sclk edges are applied before sync is brought high, the input data is also invalid. the input shift register is updated on the rising edge of sync . for another serial transfer to take place, sync must be brought low again. after the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. when the write cycle is complete, the output can be updated by taking ldac low while sync is high. readback operation the contents of the input, dac, and control registers can be read back via the sdo pin. figure 4 shows how the registers are decoded. after a register has been addressed for a read, the next 24 clock cycles clock the data out on the sdo pin. the clocks must be applied while sync is low. when sync is returned high, the sdo pin is placed in tristate. for a read of a single register, the no operation (nop) function clocks out the data. alternatively, if more than one register is to be read, the data of the first register to be addressed clocks out at the same time that the second register to be read is being addressed. the sdo pin must be enabled to complete a readback operation. the sdo pin is enabled by default. daisy-chain operation for systems that contain several devices, use the sdo pin to daisy chain several devices together. daisy-chain mode is useful in system diagnostics and in reducing the number of serial interface lines. the first falling edge of sync starts the write cycle. sclk is continuously applied to the input shift register when sync is low. if more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting the sdo of the first device to the sdi input of the next device in the chain, a multidevice interface is constructed. each device in the system requires 24 clock pulses. therefore, the total number of clock cycles must equal 24 n, where n is the total number of ad5761r / ad5721r devices in the chain. when the serial transfer to all devices is complete, sync is taken high, which latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. * additional pins omitted for clarity. controller data in sdi sclk data out serial clock control out sdo sclk sdo sclk sdo sdi sdi sync sync sync ad5761r/ ad5721r* ad5761r/ ad5721r* ad5761r/ ad5721r* 12355- 063 figure 74. daisy-chain block diagram hardware control pins load dac function ( ldac ) after data transfers into the input register of the dac, there are two ways to update the dac register and dac output. depend- ing on the status of both sync and ldac , one of two update modes is selected: synchronous dac update or asynchronous dac update.
data sheet ad5761r/ad5721r rev. a | page 27 of 35 synchronous dac update in synchronous dac update mode, ldac is held low while data is being clocked into the input shift register. the dac output is updated on the rising edge of sync . asynchronous dac update in asynchronous dac update mode, ldac is held high while data is being clocked into the input shift register. the dac output is asynchronously updated by taking ldac low after sync is taken high. the update then occurs on the falling edge of ldac . reset function ( reset ) the ad5761r / ad5721r can be reset to their power-on state by two means: either by asserting the reset pin or by using the software full reset registers (see table 26). asynchronous clear function ( clear ) the clear pin is a falling edge active input that allows the output to be cleared to a user defined value. the clearcode value is programmed by writing to bit 10 and bit 9 in the control register (see table 11 and table 12). maintain clear low for the minimum time of 20 ns to complete the operation (see figure 2). when the clear signal is returned high, the output remains at the clear value until a new value is loaded to the dac register. alert function ( alert ) when the alert pin is asserted low, a readback from the control register is required to clarify whether a short-circuit or brownout condition occurred, depending on the values of bit 12 and bit 11, the sc and bo bits, respectively (see table 15 and table 16). if neither of these conditions occurred, the temperature exceeded approximately 150c. the alert pin is low during power-up, a software full reset, or a hardware reset. after the first write to the control register to configure the dac, the alert pin is asserted high. in the event of the die temperature exceeding approximately 150c, the alert pin is low and the value of the ets bit determines the state of the digital supply of the device, whether the internal digital supply is powered on or powered down. if the ets bit is set to 0, the internal digital supply is powered on when the internal die temperature exceeds approximately 150c. if the ets bit is set to 1, the internal digital supply is powered down when the internal die temperature exceeds approximately 150c, and the device becomes nonfunctional (see table 11 and table 12). the ad5761r / ad5721r temperature at power-up must be less than 150c for proper operation of the devices. thermal hysteresis thermal hysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, to hot, and then back to ambient. thermal hysteresis data was tested for the ad5761r as shown in figure 75. it is measured by sweeping the temperature from ambient to ?40c, then to 125c, and returning to ambient. the v ref delta is then measured between the two ambient measurements (shown in figure 75). 0 1 2 3 4 5 ?120 ?100 ?80 ?60 ?40 ?20 number of hits distortion (ppm) 12355-169 figure 75. thermal hysteresis
ad5761r/ad5721r data sheet register details input shift register the input shift register is 24 bits wide. data is loaded into the device msb first as a 24 - bit word under the control of a serial clock input, sclk, which can operate at rates of up to 50 mhz. the input shift register consists of three dont care bits, one fixed value bit (db20 = 0), four address bits, and a 16 - bit or 12 - bit data - word as shown in table 8 and table 9 , respectively. table 8 . ad5761r 16 - bit input shift register format msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db [15:0] x 1 x 1 x 1 0 register address register data 1 x is dont care. table 9 . ad5721r 12 - bit input shift register format msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db[15:4] db[3:0] x 1 x 1 x 1 0 register address register data xxxx 1 1 x is dont care. table 10 . input shift register commands register address db19 db18 db17 db16 command 0 0 0 0 no operation 0 0 0 1 write to input register (no update) 0 0 1 0 update dac register from input register 0 0 1 1 write and update dac register 0 1 0 0 write to control register 0 1 0 1 no operation 0 1 1 0 no operation 0 1 1 1 software data reset 1 0 0 0 reserved 1 0 0 1 disable daisy - chain functionality 1 0 1 0 readback input register 1 0 1 1 readback dac register 1 1 0 0 readback control register 1 1 0 1 no operation 1 1 1 0 no operation 1 1 1 1 software full reset rev. a | page 28 of 35
data sheet ad5761r/ad5721r control register the control register controls the mode of operation of the ad5761r / ad5721r . the control register options are shown in table 11 and table 12. on power - up, after a full reset, or after a hardware reset, the output of the dac is clamped to ground through a 1 k ? resistor and the output buffer remains in power - down mode. a write to t he control register is required to configure the device, remove the clamp to ground, and power up the output buffer. when the dac output range is reconfigured during operation, a software full reset command (see table 26 ) must be written to the device before writing to the control register. table 11 . write to control register msb lsb db[23:21] db20 db[19:16] db[15:11] db[10:9] db8 db7 db6 db5 db[4:3] db[2:0] register address register data xxx 1 0 0100 xxxx 1 cv[1:0] ovr b2c ets iro pv[1:0] ra[2:0] 1 x is dont care. table 12 . control register functions bit name description cv[1:0] clear voltage selection. 00: zero scale 01: midscale 10, 11: full scale ovr 5% overrange. 0: 5% overrange disabled 1: 5% overrange enabled b2c bipolar range. 0: dac input for bipolar output range is straight binary coded 1: dac input for bipolar output range is twos complement coded ets thermal shutdown alert. the alert may not work correctly if the device powers on with temperature conditions >150c (greater than the maximum rating of the device). 0: internal digital supply does not power down if die temperature exceeds 150c. 1: internal digital supply powers down if die temperature exceeds 150c. iro internal reference. 0: internal reference turned off 1: internal reference turned on pv[1:0] power up voltage. 00: zero scale 01: midscale 10, 11: full scale ra[2:0] output range. after an output range configuration, the device must be reset. 000: ?10 v to +10 v 001: 0 v to +10 v 010: ?5 v to +5 v 011: 0 v to 5 v 100: ?2.5 v to +7.5 v 101: ?3 v to +3 v 110: 0 v to 16 v 111: 0 v to 20 v rev. a | page 29 of 35
ad5761r/ad5721r data sheet table 13 . bipolar output range possible codes straight binary decimal code twos complement 1111 7 0111 1110 6 0110 1101 5 0101 1100 4 0100 1011 3 0011 1010 2 0010 1001 1 0001 1000 0 0000 0111 ?1 1111 0110 ?2 1110 0101 ?3 1101 0100 ?4 1100 0011 ?5 1011 0010 ?6 1010 0001 ?7 1001 0000 ?8 1000 read b ack control register the readback control register operation provides the contents of the control register by setting the register address to 1100 . table 14 outlines the 24 - bit shift register for this command, where the last 16 bits are dont care bits. during the next command, the control register contents are shifted out of the sdo pin with the msb shifted out first. t able 15 outlines the 24 - bit data read from the sdo pin, where db23 is the first bit shifted out. table 14 . readback control register, 24 - bit shift register to the s di pin msb lsb db[23:21] db20 db[19:16] db[ 15: 0] register address register data xxx 1 0 1100 dont care 1 x is dont care. table 15 . readback control register, 24 - bit data read from the sdo pin msb lsb db[23:21] db20 db[19:16] db[15:13] db12 db11 db[10:9] db8 db7 db6 db5 db[4:3] db[2:0] register address register data xxx 1 0 1100 xxx 1 sc bo cv[1:0] ovr b2c ets iro pv[1:0] ra[2:0] 1 x is dont care. table 16 . readback control register bit descriptions bit name description sc short - circuit condition. the sc bit is reset at every control register write. 0: no short - circuit condition detected 1: short - circuit condition detected bo brownout condition. the bo bit is reset at every control register write. 0: no brownout condition detected 1: brownout condition detected rev. a | page 30 of 35
data sheet ad5761r/ad5721r update dac register from input register the update dac register function loads the dac register with the data saved in the input register and updates the dac output voltage. this operation is equivalent to a software ldac . table 17 outlines how data is written to the dac register. table 17 . update dac register from input register msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db [ 15 :0] register address register data x 1 x 1 x 1 0 0010 dont care 1 x is dont care. readback dac registe r the readback dac register operation provides the contents of the dac register by setting the register address to 1011. table 18 outlines the 24 - bit shift register for this command. during the next command, the dac register contents are shifted out of the sdo pin with t he msb shifted out first. table 19 outlines the 24 - bit data read from the sdo pin, where db23 is the first bit shifted out. table 18 . readback dac register, 24 - bit shift register to sdi pin msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db[15:0] register address register data x 1 x 1 x 1 0 1011 dont care 1 x is dont care. table 19 . readback dac register, 24 - bit data read from sdo pin msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db[15:0] register address register data x 1 x 1 x 1 0 1011 data read from dac register 1 x is dont care. write and upd ate dac register the write and update dac register (register address 0011) updates the input register and the dac register with the entered da ta - word from the input shift register, irrespective of the state of ldac . setting the register address to 0001 writes the input register with the data from the input shift register, clocked in msb first on the sdi pin. table 20 . write and update dac register msb lsb db23 db22 db21 db20 db19 db18 db17 db1 6 db[15:0] register address register data x 1 x 1 x 1 0 0001 data loaded x 1 x 1 x 1 0 0011 data loaded 1 x is dont care. rev. a | page 31 of 35
ad5761r/ad5721r data sheet readback input regis ter the readback input register operation provides the contents of the input register by setting the register address to 1010. table 21 outlines the 24 - bit shift register for this command. during the next command, the input register contents are shifted out of the sdo pin with the msb shifted out first. table 22 outlines the 24 - bit data read from the sdo pin, where db23 is the first bit shifted out. table 21 . readback input register, 24 - bit shift register to the sdi pin msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db[15:0] register address register data x 1 x 1 x 1 0 1010 dont care 1 x is dont care. table 22 . readback input register, 24 - bit data read from the sdo pin msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db[15:0] register address register data x 1 x 1 x 1 0 1010 data read from input register 1 x is dont care. disable daisy - chain functionality the daisy - chain feature can be disabled to save the power consumed by the sdo buffer when this functionality is not required (see table 23 ) . when disabled, a readback request is not accepted because the sdo pin remains in tristate. table 23 . disable daisy - chain functionality register msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db[15:1] db0 register address register data x 1 x 1 x 1 0 1001 dont care ddc 1 x is dont care. table 24 . disable daisy - chain bit description bit name description ddc ddc decides whether daisy - chain functionality is enabled or disabled for the device. by default, daisy - chain functionality is enabled. 0: daisy - chain functionality is enabled for the device. 1: daisy - chain functionality is disabled for the device. software data reset the ad5761r / ad5721r can be reset via software to zero scale, midscale, or full scale (see table 25 ). the value to which the device is reset is specified by the pv[1:0] bi ts, which are set in the write to control register command (see table 11 and table 12). table 25 . software data reset register msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db[15:0] register address register data x 1 x 1 x 1 0 0111 dont care 1 x is dont care. rev. a | page 32 of 35
data sheet ad5761r/ad5721r software full reset the device can also be reset completely via software (see table 26 ). when the register address is set to 1111, the device behaves in a power - up state, where the output is clamped to agnd and the output buffer is powered down. the user must write to the contr ol register to configure the device, remove the 1 k ? resistor clamp to ground, and power up the output buffer . the software full reset command is also issued when the dac output range is reconfigured during normal operation. table 26 . software full reset register msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db[15:0] register address register data x 1 x 1 x 1 0 1111 dont care 1 x is dont care. no operation registe rs the no operation registers are ignored and do not vary the state of the device (see table 27). table 27 . no operation register s msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db[15:0] register address register data x 1 x 1 x 1 0 0000/0101/0110/1101/1110 dont care 1 x is dont care. rev. a | page 33 of 35
ad5761r/ad5721r data sheet rev. a | page 34 of 35 applications information typical operating circuit figure 76 shows the typical operating circuit for the ad5761r / ad5721r . the only external components needed for this precision 16-/12-bit dac are decoupling capacitors on the supply pins and supply voltage. because the ad5761r / ad5721r incorporate a voltage reference and reference buffers, they eliminate the need for an external bipolar reference and associated buffers, resulting in overall savings in both cost and board space. in figure 76, v dd is connected to 15 v and v ss is connected to ?15 v, but v dd and v ss can operate with supplies from 4.75 v to 30 v and from ?16.5 v to 0 v, respectively. 1 2 3 4 5 6 7 8 v out ?15v 10f 10f 100nf 100nf v refin +15v 16 15 14 13 12 11 10 9 sdi dgnd sdo dv cc dnc sclk ad5761r / ad5721r sync clear reset ldac sdi sdo sclk sync ldac alert agnd v out v ss v dd clear reset alert + 100nf 10f +5v 12355- 064 v refin / v refout notes 1. dnc = do not connect. do not connect to this pin. figure 76. typical operating circuit power supply considerations the ad5761r / ad5721r must be powered by the following three supplies to provide any of the eight output voltage ranges available on the dac: v dd = 21 v, v ss = ?11 v, and dv cc = 5 v. for applications requiring optimal high power efficiency and low noise performance, it is recommended to use the adp5070 switching regulator to convert the 5 v input rail into two intermediate rails (+23 v and ?13 v). these intermediate rails are then postregulated by very low noise, low dropout (ldo) regulators ( adp7142 and adp7182 ). figure 77 shows the recommended method. adp7182 ldo ?11v: vss adp7142 ldo +5v: dvcc adp7142 ldo +21v: vdd +5v input +23v ?13v +5v input 12355-070 adp5070 dc-to-dc switching regulator adp5070 dc-to-dc switching regulator figure 77. postregulation by adp7142 and adp7182 evaluation board an evaluation board is available for the ad5761r to aid designers in evaluating the high performance of the device with minimum effort. the ad5761r evaluation kit includes a populated and tested ad5761r printed circuit board (pcb). the evaluation board interfaces to the usb port of a pc. software is available with the evaluation board to allow the user to easily program the ad5761r . the eval-ad5761rsdz user guide provides full details on the operation of the evaluation board.
data sheet ad5761r/ad5721r rev. a | page 35 of 35 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 78. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. figure 79. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm 3 mm body, very very thin quad (cp-16-22) dimensions shown in millimeters ordering guide model 1 resolution (bits) internal reference (v) temperature range inl (lsb) package description package option branding ad5721rbruz 12 2.5 ?40c to +125c 0.5 16-lead tssop ru-16 ad5721rbruz-rl7 12 2.5 ?40c to +125c 0.5 16-lead tssop ru-16 ad5721rbcpz-rl7 12 2.5 ?40c to +125c 0.5 16-lead lfcsp_wq cp-16-22 dhn ad5761raruz 16 2.5 ?40c to +125c 8 16-lead tssop ru-16 ad5761raruz-rl7 16 2.5 ?40c to +125c 8 16-lead tssop ru-16 ad5761rbruz 16 2.5 ?40c to +125c 2 16-lead tssop ru-16 ad5761rbruz-rl7 16 2.5 ?40c to +125c 2 16-lead tssop ru-16 AD5761RACPZ-RL7 16 2.5 ?40c to +125c 8 16-lead lfcsp_wq cp-16-22 dj5 ad5761rbcpz-rl7 16 2.5 ?40c to +125c 2 16-lead lfcsp_wq cp-16-22 dj6 eval-ad5761rsdz evaluation board 1 z = rohs compliant part. ?2014C2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12355-0-5/15(a)

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